Integrated circuits (ICs) typically include a plurality of semiconductor devices including interconnect wiring. Networks of metal interconnect wiring are often used to connect the semiconductor devices from the semiconductor portion of the substrate. Multiple levels of metal interconnect wiring above the semiconductor portion of the substrate are connected together to form a back-end-of-the-line (“BEOL”) interconnect structure. Within such a structure, metal lines run parallel to the substrate and conductive vias run perpendicular to the substrate. The conductive vias typically interconnect the different levels of the metal wiring levels.
High performance of contemporary ICs may be achieved using a highly conductive metal, such as copper, as the interconnect metal of the BEOL interconnect structure, which also employs a low dielectric constant material or dielectric material as an interlevel dielectric (ILD) layer or layers. The dielectric material may be non-porous, porous or a combination of porous and non-porous. To help hold the highly conductive interconnect metal to the dielectric material, a metal liner material, such as tantalum or tantalum nitride, is deposited onto the dielectric material to form a metal liner layer. Then, a conductive metal seed layer, such as a layer of copper or copper alloy, is formed on the metal liner layer and the highly conductive metal is deposited over the conductive metal seed layer to form a metal interconnect wire.
Unfortunately, the metal liner material has a relatively high resistivity compared to the highly conductive metal and thus, can effectively decrease the overall conductivity of the metal interconnect wire. Additionally, because the feature sizes of many elements on semiconductor devices are steadily decreasing with the introduction of newer semiconductor technologies, it is desirable to reduce or minimize the thickness of the metal liner layer to increase the cross-sectional area of the highly conductive metal to preferably maximize the conductivity of the metal interconnect wire without adversely affecting any packaging space requirements. However, controllably forming a very thin metal layer for a semiconductor device using current approaches can be challenging because even at low rates of depositing the metal material onto the dielectric material, small variations in the deposition time can result in relatively large differences in the thickness of the metal layer. Moreover, controllably forming a very thin metal layer to continuously cover a dielectric material that has a relatively rough surface, e.g., a surface of a porous dielectric material, using current approaches further exacerbates this challenge.
Accordingly, it is desirable to provide methods for forming a semiconductor device including controllably forming a very thin metal layer that may function, for example, as a metal liner layer or other semiconductor metal layer structure. Moreover, it is desirable to provide methods for forming a semiconductor device including controllably forming a very thin metal layer to continuously cover a dielectric material that has a relatively rough surface. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background of the invention.